This invention relates to an integrated circuit structure which comprises a power circuit portion and a control circuit portion and is free from parasitic currents.
In an integrated electronic structure including a power circuit portion, specifically a bipolar type of power device with a vertical current flow, and a control circuit portion, such as a P-type region, a parasitic PNP transistor is created between the base of the power device and the P region.
FIG. 1 shows a conventional integrated circuit 1xe2x80x2 comprising a semiconductor substrate 2xe2x80x2 of the N-type which is formed with a first well 3xe2x80x2 of the P type provided for forming a power device, and a second well 4xe2x80x2, also of the P type, comprising a control region.
In particular, where a bipolar power transistor Power is to be provided, a third well 5xe2x80x2 of the N type is formed inside the first well 1xe2x80x2, in which the emitter terminal for the bipolar power transistor Power can be formed. The power transistor Power will have its collector terminal in the semiconductor substrate 2xe2x80x2 and its base terminal in the first well 3xe2x80x2.
A fourth wall 6xe2x80x2, also of the N type, is likewise formed inside the second well 4xe2x80x2 and may be connected to a supply voltage reference Vcc, for example.
Consequently, the integrated circuit 1xe2x80x2 will include a first parasitic transistor P1, whose emitter terminal is coincident with the base terminal of the bipolar transistor Power, i.e., with the first well 3xe2x80x2. The base terminal of this parasitic transistor is coincident with the collector terminal of the bipolar power transistor Power, i.e., with the semiconductor substrate 2xe2x80x2, and its collector terminal is coincident with the second well 4xe2x80x2 facing the bipolar power transistor Power.
In order for the first parasitic transistor P1 to be turned off, the value of the potential applied to its base terminal must be at least equal to, or higher than, the value of the potential applied to its emitter terminal.
This condition is always met when the power device Power is operated in the linear range. But in most applications, the power device Power will be operated actually in the saturation range, since it is to serve a switching function.
Under this operating condition, the base-collector junction of the bipolar power transistor Power, and hence the emitter-base junction of the first parasitic transistor P1, would be forward biased.
There practically occurs a current injection from the first well 3xe2x80x2, where the power transistor is formed, to the second well 4xe2x80x2. The value of this current is a function of the gain of the first parasitic transistor P1.
The appearance of this current in the second well 4xe2x80x2 causes malfunctioning, of the control logic of the integrated circuit 1xe2x80x2. For the integrated circuit 1xe2x80x2 to operate correctly, it is necessary that the potential at the second well 4xe2x80x2 be lower than, or equal to, the potential at the semiconductor substrate 2xe2x80x2 in which the bipolar power transistor Power and control circuit portion are both formed. It is only by meeting this restriction on potentials that the turning on of a second parasitic transistor P2, having its base terminal coincident with the second well 4xe2x80x2, emitter terminal coincident with the semiconductor substrate 2xe2x80x2, and collector terminal coincident with the fourth well 6xe2x80x2, can be prevented.
It should be considered, in particular, that the second well 4xe2x80x2 is essentially biased to a reference value Visas through a resistive path which is represented by a resistive element R1. The injected current from the turning on of the first parasitic transistor P1 obeys the following relation;
Vbias+R1*Ixe2x88x92V(2)=VbeP2xe2x80x83xe2x80x83(1)
where,
Vbias is the bias voltage of the second well 4xe2x80x2;
R1 is the resistance of the resistive path inside the second well 4xe2x80x2;
I is the current injected into the second well 4xe2x80x2 from the turning on of the first parasitic transistor P1;
V(2) is the value of the potential applied to the semiconductor substrate 2xe2x80x2; and
VbeP2 is the base-emitter voltage of the second parasitic transistor P2;
the parasitic transistor P2 is turned on, causing malfunction to occur in the control region of the integrated circuit.
A first known technical solution to the problem posed by the presence of parasitic transistors provides for that area of the semiconductor substrate 2xe2x80x2 that lies intermediate between the first well 3xe2x80x2 and the second 4xe2x80x2 to be doped more heavily. In this way, the gain of the first parasitic transistor P1 is reduced.
However, this doping must not be carried too far, if the integrated circuit 1xe2x80x2 is to be held at the correct voltage. In addition, the flow of current between the wells of the P type is reduced but not eliminated, with this solution.
A second solution provides for increased spacing of the P-wells. However, not even this solution ig effective to suppress the flow of current brought about by the turning on of parasitic transistors.
A third solution provides for an intermediate region 7xe2x80x2, also of the P type, to be included between the aforementioned P-wells, as shown schematically in FIG. 2.
Unfortunately, this solution also has several drawbacks:
First, where the intermediate region 7xe2x80x2 is a floating region, a self-biasing of the intermediate region 7xe2x80x2 to the value of potential of the first well 3xe2x80x2 is precipitated upon a parasitic PNP transistor P1xe2x80x2, associated with the well 3xe2x80x2 and the intermediate region 7xe2x80x2, entering its saturation range. As a result, an additional parasitic transistor P1xe2x80x3, associated with the second well 4xe2x80x2 and tho region 7xe2x80x2, is caused to move into its conduction range. The net effect of providing this intermediate region 7xe2x80x2 is one of lowering the current gain of the parasitic elements as a whole: the net effect of the parasitic components is split between the two transistors, P1xe2x80x2 and P1xe2x80x3, but one (P1xe2x80x2) of them will be in its saturation range.
Second, when the intermediate reio 7xe2x80x2 is connected to a voltage reference, e.g., to ground, and by reason of the application involved the second well 4xe2x80x2 is biased to a potential level below ground, the parasitc transistor P1xe2x80x3 will move into its conduction range and draw current from the ground reference terminal to the second well 4xe2x80x2.
Therefore the prior art does not adequately solve the problems of parasitic flow of current in these types of integrated circuits due to parasitic components.
Presented is an integrated circuit comprising a power device and a control region that has structural and functional features that eliminates the parasitic flow of current. The circuit is formed on a semiconductor substrate with conductivity of a first type, and incorporates a first circuit portion incorporated in a first well that includes at least one power transistor. The circuit also has a control circuit portion incorporated in a second well, and an intermediate region located between the first and second circuit portions. The conductivity of the first well, second well, and intermediate region are all of a second type. The intermediate region between the wells is biased as a function of the potential of the well wherein the power device is formed.
The features and advantages of an integrated circuit structure according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.